Silicon-germanium (SiGe) and silicon-carbide (SiC) processing has been considered as a performance booster for p-type metal-oxide silicon (PMOS) and n-type metal-oxide silicon (NMOS) transistors in 40 nm technology and more advanced nodes, such as 28 nm, 22 nm and 20 nm. SiGe and SiC processing is frequently used in memory arrays such as static random access memory (SRAM) arrays to boost the performance of PMOS and NMOS transistors of the word line (WL) drivers.
FIG. 1A is layout of a WL driver 100 formed on a semiconductor substrate 102. WL driver 100 includes long active areas 104-1, 104-2 (collectively referred to as “active areas 104”) extending across the semiconductor chip from one edge 102a abutting a first shallow trench isolation (STI) region 110 (FIG. 1C) to an opposite edge abutting a second STI region 110. A plurality of polysilicon (poly) fingers 106 are formed over active areas 104 with each poly finger 106 respectively defining a transistor with active areas 104. For example, each poly silicon finger 106 forms the gate of a PMOS transistor with active area 104-1, which includes the source and drain regions, and each poly silicon finger 106 forms the gate of an NMOS transistor with active area 104-2, which includes the source and drain regions. A pair of dummy poly segments 108 are disposed adjacent to an edge 102a of the chip 102 over a shallow trench isolation (STI) region 110. Due to the limitations of the lithography processing, two dummy poly segments 108 are included at each edge of substrate 102 to help ensure that the active poly fingers 106 are properly formed.
However, the conventional layout of a WL driver 100 formed by a SiGe or SiC process suffers from faceting at the edges of the active areas 104 as best seen in FIG. 1C, which is a cross-sectional view of the simplified illustration of active area 104-1 shown in FIG. 1B. As shown in FIG. 1C, active area 104-1 includes a plurality of SiGe or SiC areas 114, 116 with the edge SiGe or SiC areas 116 including a facet 118, i.e., an undercut area. Facets 118 reduce the carrier mobility of the transistor formed by the source and drain regions (not shown) in active area 104-1 and poly gate 112. The reduction in carrier mobility significantly degrades the performance of the edge transistors.
Accordingly, an improved layout of an edge transistor is desirable.